1. Field of the Invention
Embodiments of the present invention generally relate to semiconductor manufacturing. More specifically, embodiments of the present invention relate to a method and a system for identifying locations in a layout of an integrated circuit (IC) chip that are susceptible to manufacturing errors.
2. Related Art
Advances in IC manufacturing technology have enabled minimum feature sizes on IC chips to continuously decrease. In fact, the current minimum feature size is smaller than the wavelengths of light used in conventional optical imaging systems. Accordingly, it is becoming increasingly difficult to achieve reasonable fidelity, which is often expressed in resolution and depth of focus, between a designed layout and the shapes of actual fabricated circuit elements. Existing reticle enhancement technologies (RETs), such as optical proximity correction (OPC), phase-shifting masks (PSMs), and sub-resolution assist features (SRAFs), are becoming inadequate to solve fabrication issues on the nanometer scale.
Manufacturability-aware physical design, which takes into account both yield and reliability during the physical-design process, is becoming increasingly important in bridging the gap between design and manufacturing for nanometer-scale fabrication processes. Many yield and reliability issues can be attributed to certain layout configurations, referred to as “process-hotspots” or “hotspots,” which are susceptible to process issues, such as stress and lithographic process fluctuations. It is therefore desirable to identify and remove these process-hotspot configurations and replace them with more yield-friendly configurations.
Conventionally, layout design engineers use manufacturer-provided design rules to represent localized process-hotspots. A typical design rule checker can detect such process-hotspots within the layout, which facilitates making corrections to the process-hotspots to be compliant with the rules. However, design rules are not sufficient to detect process-hotspots caused by a set of closely arranged objects occupying a larger layout region (e.g., a 1×1 μm2 region). Note that these “large” hotspots typically arise from a “proximity effect,” which is an aggregated physical effect (that can include lithography effects and mechanical stress effects) from a particular layout configuration of a set of geometries in proximity to each other. Because of the complexity of the processes involved in the proximity effect, these proximity-effect-induced hotspots cannot effectively be described by a set of design rules.
To address this problem, a new type of hotspot-description technique referred to as “pattern clips” has been introduced by manufacturers. Note that instead of using design rules, a pattern clip provides a straightforward image-based representation of a layout configuration that can cause a process-hotspot. Note that manufacturers can routinely publish new “pattern clips” to make them available to designers to detect hotspots. Accordingly, designers can use pattern-matching techniques to identify these pattern clips in design layouts.
Unfortunately, automatic techniques for modifying a layout to resolve the identified pattern-clip-based hotspots are typically not available to the designers. Note that a pattern clip by itself is not sufficient for designers to make correction decisions for the identified hotspots. This is because each hotspot is caused by the proximity effect associated with the entire pattern clip, and the hotspot image does not indicate which of the constituent geometries need to be altered to remove or reduce the degree of the hotspot.
Hence, there is a need for a technique to automatically correct pattern-clip-based hotspots in a layout when they are identified.